SmartCam Design Framework

The last few years have seen the advent of Smart Cameras, surveillance-camera sized devices with onboard programmable logic. Usually, Digital Signal Processors (DSPs) or general-purpose (GP) microprocessors are used, but obviously the specific field of image processing allows for many architectural optimizations, such as the use of single-instruction multiple-data (SIMD) processors for filtering. Furthermore, intuitive mappings of algorithms on architecture components are used, after the architecture has been determined. It will be clear that this is far from optimal. Finally we foresee a further integration, making a combination of on-chip vision sensor, pixel processing, control, and feature / object processing possible. The result is a low-cost one-chip smart camera (so-called SmartCam) solution. This means that research is needed to explore the new architectural opportunities and consequences. The SmartCam project investigates these new opportunities and contributes to a better and more quantitatively guided design trajectory. This paper describes the design flow as seen by the application developer: the use of algorithmic skeletons to exploit data-parallelism, and design space exploration to find a suitable boardand processor architecture. We explain how it can lead to smaller, cheaper, and more efficient devices, tailored to a specific application or set of applications.